Efficacité d’apprentissage à partir d’un Business Simulation Game : vers une nouvelle approche sociomatérielle

Les business simulation games connaissent un véritable essor en milieu éducatif et pourtant nous avons que peu de recul sur leurs usages en tant que dispositifs de formation. Dans l’enseignement supérieur, ceux-ci sont mis en place pour faciliter le transfert des connaissances et atteindre des objectifs pédagogiques. Cependant, l’utilisation des business simulation games en tant que dispositifs de formation montre qu’il existe un certain nombre d’aspects susceptibles d’influencer l’apprentissage des étudiants de manière générale. Cette étude de cas d’un établissement d’enseignement supérieur basé sur un échantillon de 52 étudiants, s’appuie sur une méthodologie mixte montrant que l’apprentissage via un business simulation game est un processus dynamique qui permet de retenir davantage de connaissances sur le sujet abordé. Egalement, nous mobilisons l’approche sociomatérielle qui offre la possibilité de comprendre le processus d’apprentissage comme un ensemble imbriqué de pratiques sociomatérielles. Ce travail est basé sur une méthode mixte qui combine une dimension qualitative et quantitative. A partir d’une étude de cas sur un business simulation game destiné à l’apprentissage des fondamentaux de la gestion d’entreprise, nous étudions les éléments qui améliorent l’efficacité d’apprentissage chez les étudiants. Nos résultats mettent en évidence un certain nombre d’éléments qui influencent l’efficacité d’apprentissage comme la formation, qualité du système d’information, communication et utilité perçue

A high sensitivity and low power circuit for the measurement of abnormal blood cell levels

This paper describes a technique to detect blood cell levels based on the time-period modulation of a relaxation oscillator loaded with an Inter Digitated Capacitor (IDC). A digital readout circuit has been proposed to measure the time-period difference between the two oscillators loaded with samples of healthy and (potentially) unhealthy blood. A prototype circuit was designed in 65nm CMOS technology and post-layout simulations shows 15.25aF sensitivity. The total circuit occupies 2184µm2 silicon area and consumes 216µA from a 1V power supply

Deep and transfer learning for building occupancy detection: A review and comparative analysis

The building internet of things (BIoT) is quite a promising concept for curtailing energy consumption, reducing costs, and promoting building transformation. Besides, integrating artificial intelligence (AI) into the BIoT is essential for data analysis and intelligent decision-making. Thus, data-driven approaches to infer occupancy patterns usage are gaining growing interest in BIoT applications. Typically, analyzing big occupancy data gathered by BIoT networks helps significantly identify the causes of wasted energy and recommend corrective actions. Within this context, building occupancy data aids in the improvement of the efficacy of energy management systems, allowing the reduction of energy consumption while maintaining occupant comfort. Occupancy data might be collected using a variety of devices. Among those devices are optical/thermal cameras, smart meters, environmental sensors such as carbon dioxide (CO2), and passive infrared (PIR). Even though the latter methods are less precise, they have generated considerable attention owing to their inexpensive cost and low invasive nature. This article provides an in-depth survey of the strategies used to analyze sensor data and determine occupancy. The article's primary emphasis is on reviewing deep learning (DL), and transfer learning (TL) approaches for occupancy detection. This work investigates occupancy detection methods to develop an efficient system for processing sensor data while providing accurate occupancy information. Moreover, the paper conducted a comparative study of the readily available algorithms for occupancy detection to determine the optimal method in regards to training time and testing accuracy. The main concerns affecting the current occupancy detection system in terms of privacy and precision were thoroughly discussed. For occupancy detection, several directions were provided to avoid or reduce privacy problems by employing forthcoming technologies such as edge devices, Federated learning, and Blockchain-based IoT. 2022 The AuthorsThis paper was made possible by the Graduate Assistant-ship (GA) program provided from Qatar University (QU). The statements made herein are solely the responsibility of the authors. Open Access funding provided by the Qatar National Library.Scopu

Nonlinear Control and Synchronization with Time Delays of Multiagent Robotic Systems

We investigate the cooperative control and global asymptotic synchronization Lagrangian system groups, such as industrial robots. The proposed control approach works to accomplish multirobot systems synchronization under an undirected connected communication topology. The control strategy is to synchronize each robot in position and velocity to others robots in the network with respect to the common desired trajectory. The cooperative robot network only requires local neighbor-to-neighbor information exchange between manipulators and does not assume the existence of an explicit leader in the team. It is assumed that network robots have the same number of joints and equivalent joint work spaces. A combination of the lyapunov-based technique and the cross-coupling method has been used to establish the multirobot system asymptotic stability. The developed control combines trajectory tracking and coordination algorithms. To address the time-delay problem in the cooperative network communication, the suggested synchronization control law is shown to synchronize multiple robots as well as to track given trajectory, taking into account the presence of the time delay. To this end, Krasovskii functional method has been used to deal with the delay-dependent stability problem

A start-up assisted fully differential folded cascode opamp

This paper explains the hidden positive feedback in the two-stage fully differential amplifier through external feedback resistors, and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascode branches have been explained intuitively, With reference to previous literature. To avoid the latch-up problem irrespective of the transistor bias currents a novel, hysteresis based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126uA from a 1.2V supply and occupies the 2184um2 area

An OTA gain enhancement technique for low power biomedical applications

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area

Simulation of driver fatigue monitoring via blink rate detection, using 65nm CMOS technology

This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130uA from a 1.2V power supply

A 0.82V supply and 23.4 ppm/0C current mirror assisted bandgap reference

Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area

A 261mV bandgap reference based on beta multiplier with 64ppm

In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV

A low noise amplifier suitable for biomedical recording analog front-end in 65nm CMOS technology

This paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area